In the communication field, a frequency divider is required for the realization of clock frequency division, wherein the principle of the frequency divider is that: each time when int(Σb) is accumulated to be an integer, the frequency divider will add an input clock cycle Ti to frequency division time of an output clock cycle To according to Formula (1), which will shorten the output clock cycle To.ΣTo=(Σa+int(Σb))*Ti+mod(Σb)*Ti  (1)
Wherein, mod indicates a modulus function, int indicates an integral function, Ti represents the input clock cycle, to represents the output clock cycle, a is an integer portion after frequency division processing, and b is a decimal portion after frequency division processing.
In practical application, the decimal portion b after the frequency division processing performed by the frequency divider is generally separated to be processed as an integer portion, which can be applied in network communications, such as the circuit emulation service of the packet switch network, so as to recover the clock of the source end at the receiver terminals.
At present, the specific method for decimal frequency division is as follows.
First of all, the integer portion ai and the decimal portion bi of the current frequency division are determined according to a current frequency division coefficient Ki in Formula (2), and a decimal scale threshold ci is determined according to the determined decimal portion bi. As required by the precision, the decimal portion bi can be represented by an 8-bit, 12-bit, 16-bit or 32-bit value, etc., for example, if the decimal portion bi is a hexadecimal value, the corresponding decimal scale threshold ci is 3B9ACA00.
                              K          ⁢                                          ⁢          i                =                                            F              ⁢                                                          ⁢              i                                      F              ⁢                                                          ⁢              o                                =                                                    T                ⁢                                                                  ⁢                o                                            T                ⁢                                                                  ⁢                i                                      =                                          a                ⁢                                                                  ⁢                i                            +                              b                ⁢                                                                  ⁢                i                                                                        (        2        )            
Then the output clock frequency Fo is obtained based on the input clock frequency Fi according to the Formula (2) with the determined integer portion ai of the current frequency division, decimal portion bi of the current frequency division and current value of the decimal scale threshold ci of the current frequency division, so as to recover the clock frequency of the source end at the receiver terminals.
The clock frequency division method above is completed on the basis of the hypothesis that the frequency division coefficient Ki is fixed. It can be used only in the situation where the frequency division coefficient is fixed; moreover, the decimal portion bi generally supports the value precision of 1 bit or 2 bits only. The frequency division precision is low, which makes it hard to meet the requirements of high frequency division precision, multi bit decimal portion and the dynamic adjustment of the frequency division coefficient in the clock recovery application in the communication field such as the packet switch network.